Datasheet

8 Datasheet, Volume 2
4.4.3.2 Compatible Revision ID (CRID) .................................................203
4.4.4 CCR—Class Code Register......................................................................204
4.4.5 HDR—Header Type Register ...................................................................205
4.4.6 SVID—Subsystem Vendor Identification Register.......................................205
4.4.7 SID—Subsystem Identity.......................................................................206
4.4.8 PCICMD—Command Register..................................................................207
4.4.9 PCISTS—PCI Status Register..................................................................208
4.5 SAD—System Address Decoder Registers............................................................209
4.5.1 SAD_PAM0123 .....................................................................................209
4.5.2 SAD_PAM456.......................................................................................211
4.5.3 SAD_HEN ............................................................................................212
4.5.4 SAD_SMRAM........................................................................................212
4.5.5 SAD_PCIEXBAR....................................................................................213
4.5.6 SAD_TPCIEXBAR ..................................................................................213
4.5.7 SAD_MCSEG_BASE...............................................................................214
4.5.8 SAD_MCSEG_MASK ..............................................................................214
4.5.9 SAD_MESEG_BASE ...............................................................................215
4.5.10 SAD_MESEG_MASK...............................................................................215
4.5.11 SAD_DRAM_RULE_0; SAD_DRAM_RULE_1
SAD_DRAM_RULE_2; SAD_DRAM_RULE_3
SAD_DRAM_RULE_4; SAD_DRAM_RULE_5
SAD_DRAM_RULE_6; SAD_DRAM_RULE_7...............................................216
4.5.12 SAD_INTERLEAVE_LIST_0; SAD_INTERLEAVE_LIST_1
SAD_INTERLEAVE_LIST_2; SAD_INTERLEAVE_LIST_3
SAD_INTERLEAVE_LIST_4; SAD_INTERLEAVE_LIST_5
SAD_INTERLEAVE_LIST_6; SAD_INTERLEAVE_LIST_7...............................217
4.6 Intel
®
QuickPath Interconnect Link Registers.......................................................218
4.6.1 QPI_QPILCL_L0....................................................................................218
4.7 Integrated Memory Controller Control Registers...................................................220
4.7.1 MC_CONTROL ......................................................................................220
4.7.2 MC_SMI_DIMM_ERROR_STATUS.............................................................221
4.7.3 MC_SMI_CNTRL....................................................................................221
4.7.4 MC_STATUS.........................................................................................222
4.7.5 MC_RESET_CONTROL............................................................................222
4.7.6 MC_CHANNEL_MAPPER..........................................................................223
4.7.7 MC_MAX_DOD......................................................................................223
4.7.8 MC_CFG_LOCK.....................................................................................224
4.7.9 MC_RD_CRDT_INIT...............................................................................225
4.7.10 MC_CRDT_WR_THLD.............................................................................226
4.8 TAD—Target Address Decoder Registers .............................................................227
4.8.1 TAD_DRAM_RULE_0; TAD_DRAM_RULE_1
TAD_DRAM_RULE_2; TAD_DRAM_RULE_3
TAD_DRAM_RULE_4; TAD_DRAM_RULE_5
TAD_DRAM_RULE_6; TAD_DRAM_RULE_7 ...............................................227
4.8.2 TAD_INTERLEAVE_LIST_0; TAD_INTERLEAVE_LIST_1
TAD_INTERLEAVE_LIST_2; TAD_INTERLEAVE_LIST_3
TAD_INTERLEAVE_LIST_4; TAD_INTERLEAVE_LIST_5
TAD_INTERLEAVE_LIST_6; TAD_INTERLEAVE_LIST_7...............................228
4.9 Integrated Memory Controller Test Registers.......................................................229
4.9.1 Integrated Memory Controller Padscan ....................................................229
4.9.2 MC_DIMM_CLK_RATIO_STATUS .............................................................231
4.9.3 MC_DIMM_CLK_RATIO ..........................................................................232
4.9.4 MC_TEST_LTRCON................................................................................232
4.9.5 MC_TEST_PH_CTR................................................................................233
4.9.6 MC_TEST_PH_PIS.................................................................................233
4.9.7 MC_TEST_PAT_GCTR ............................................................................234
4.9.8 MC_TEST_PAT_BA ................................................................................235