Datasheet

Processor Integrated I/O (IIO) Configuration Registers

74 Datasheet, Volume 2

3.3.4.29 DEVCTRL2—PCI Express* Device Control Register 2

Device: 0 (DMI), 3, 5 (PCIe)

Function: 0

Offset: B8h

Bit Attr Default Description

15:6 RO 0h Reserved

5RW 0

Alternative RID Interpretation (ARI) Enable

When set to 1b, ARI is enabled for the Root Port.

4RW 0

Completion Time-out Disable

1 = Disables the Completion Time-out mechanism for all NP tx that IIO issues

on the PCI Express/DMI link.

0 = Completion time-out is enabled.

Software can change this field while there is active traffic in the root port.

3:0 RW 0000b

Completion Time-out Value on NP Tx that Integrated I/O Issues on

PCI Express/DMI – In Devices that support Completion Time-out

programmability, this field allows system software to modify the Completion

Time-out range. The following encodings and corresponding time-out ranges

are defined:

0000b = 10 ms to 50 ms

0001b = Reserved (Integrated I/O aliases to 0000b)

0010b = Reserved (Integrated I/O aliases to 0000b)

0101b = 16 ms to 55 ms

0110b = 65 ms to 210 ms

1001b = 260 ms to 900 ms

1010b = 1 s to 3.5 s

1101b = 4 s to 13 s

1110b = 17 s to 64 s

When the OS selects 17 s to 64 s range, the CTOCTRL register further controls

the time-out value within that range. For all other ranges selected by OS, the

time-out value within that range is fixed in Integrated I/O hardware.

Software can change this field while there is active traffic in the root port.