Datasheet

Datasheet, Volume 2 73

Processor Integrated I/O (IIO) Configuration Registers

3.3.4.28 DEVCAP2—PCI Express* Device Capabilities Register 2

Device: 0 (DMI), 3, 5 (PCIe)

Function: 0

Offset: B4h

Bit Attr Default Description

31:6 RO 0h Reserved

5RO 1

Alternative RID Interpretation (ARI) Capable

This bit is set to 1b indicating Root Port supports this capability.

4RO 1

Completion Time-out Disable Supported

IIO supports disabling completion time-out.

3:0 RO 1110b

Completion Time-out Values Supported

This field indicates device support for the optional Completion Time-out

programmability mechanism. This mechanism allows system software to

modify the Completion Time-out range. Bits are one-hot encoded and set

according to the table below to show time-out value ranges supported. A

device that supports the optional capability of Completion Time-out

Programmability must set at least two bits.

Four time values ranges are defined:

A: 50 µs to 10 ms

B: 10 ms to 250 ms

C: 250 ms to 4 s

D: 4 s to 64 s

Bits are set according to table below to show time-out value ranges supported.

0000b = Completions Time-out programming not supported -- values is fixed

by implementation in the range 50 µs to 50 ms.

0001b = Range A

0010b = Range B

0011b = Range A & B

0110b = Range B & C

0111b = Range A, B, & C

1110b = Range B, C, & D

1111b = Range A, B, C & D

All other values are reserved.

Integrated I/O supports time-out values up to 10 ms-64 s.