Datasheet

Datasheet, Volume 2 71

Processor Integrated I/O (IIO) Configuration Registers

3.3.4.26 ROOTCAP—PCI Express* Root Capabilities Register

The PCI Express Root Status register specifies parameters specific to the root complex

port.

0RW 0h

System Error on Correctable Error Enable

This field controls notifying the internal core error logic of the occurrence of a

correctable error in the device or below its hierarchy. The internal core error

logic of Integrated I/O then decides if/how to escalate the error further

(pins/message, and so forth).

0 = No internal core error logic notification should be generated on a

correctable error reported by any of the devices in the hierarchy

associated with and including this port.

1 = Indicates that an internal core error logic notification should be generated

if a correctable error is reported by any of the devices in the hierarchy

associated with and including this port.

Note that generation of system notification on a PCI Express correctable error

is orthogonal to generation of an MSI interrupt for the same error. Both a

system error and MSI can be generated on a correctable error or software can

choose one of the two.

Refer to the latest PCI Express Base Specification for details of how this bit is

used in conjunction with other error control bits to generate core logic

notification of error events in a PCI Express/DMI port.

(Sheet 2 of 2)

Device: 0 (DMI), 3, 5 (PCIe)

Function: 0

Offset: ACh

Bit Attr Default Description

Device: 0 (DMI), 3, 5 (PCIe)

Function: 0

Offset: AEh

Bit Attr Default Description

15:1 RV 0h Reserved

0RO 1

CRS Software Visibility

When set to 1, this bit indicates that the Root Port is capable of returning

Configuration Request Retry Status (CRS) Completion Status to software.

Integrated I/O supports this capability.