Datasheet

Processor Integrated I/O (IIO) Configuration Registers
70 Datasheet, Volume 2
3.3.4.25 ROOTCON—PCI Express* Root Control Register
The PCI Express Root Control register specifies parameters specific to the root complex
port.
(Sheet 1 of 2)
Register: ROOTCON
Device: 0 (DMI), 3, 5 (PCIe)
Function: 0
Offset: ACh
Bit Attr Default Description
15:5 RV 0h Reserved
4RW 0h
CRS Software Visibility Enable
When set to 1, this bit enables the Root Port to return Configuration Request
Retry Status (CRS) Completion Status to software. If 0, retry status cannot be
returned to software. Root ports that do not implement this capability must
hardwire this bit to 0b.
3RW 0h
PME Interrupt Enable
This field controls the generation of MSI interrupts and Intx messages for PME
messages.
0 = Disables interrupt generation for PME messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected
in the PME status bit of the Root Status Register.
2RW 0h
System Error on Fatal Error Enable
This field enables notifying the internal core error logic of occurrence of an
uncorrectable fatal error at the port or below its hierarchy. The internal core
error logic of Integrated I/O then decides if/how to escalate the error further
(pins/message, an so forth).
0 = No internal core error logic notification should be generated on a fatal
error reported by any of the devices in the hierarchy associated with and
including this port.
1 = Indicates that a internal core error logic notification should be generated
if a fatal error is reported by any of the devices in the hierarchy
associated with and including this port.
Note that generation of system notification on a PCI Express/DMI fatal error is
orthogonal to generation of an MSI interrupt for the same error. Both a system
error and MSI can be generated on a fatal error or software can choose one of
the two.
Refer to the latest PCI Express Base Specification for details of how this bit is
used in conjunction with other error control bits to generate core logic
notification of error events in a PCI Express/DMI port.
1RW 0h
System Error on Non-Fatal Error Enable
This field enables notifying the internal core error logic of occurrence of an
uncorrectable non-fatal error at the port or below its hierarchy. The internal
core error logic of Integrated I/O then decides if/how to escalate the error
further (pins/message and so forth).
0 = No internal core error logic notification should be generated on a non-
fatal error reported by any of the devices in the hierarchy associated with
and including this port
1 = Indicates that a internal core error logic notification should be generated
if a non-fatal error is reported by any of the devices in the hierarchy
associated with and including this port.
Note that generation of system notification on a PCI Express/DMI non-fatal
error is orthogonal to generation of an MSI interrupt for the same error. Both a
system error and MSI can be generated on a non-fatal error or software can
choose one of the two.
Refer to the latest PCI Express Base Specification for details of how this bit is
used in conjunction with other error control bits to generate core logic
notification of error events in a PCI Express/DMI port.