Datasheet

Processor Integrated I/O (IIO) Configuration Registers
66 Datasheet, Volume 2
3.3.4.22 LNKSTS—PCI Express* Link Status Register
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training, and so forth.
(Sheet 1 of 2)
Register: LNKSTS
Device: 0 (DMI), 3, 5 (PCIe)
Function: 0
Offset: A2h
Bit Attr Default Description
15 RW1C 0
Link Autonomous Bandwidth Status
This bit is set to 1 by hardware to indicate that hardware has
autonomously changed link speed or width, without the port transitioning
through DL_Down status, for reasons other than to attempt to correct
unreliable link operation.
Integrated I/O sets this bit when it receives eight consecutive TS1 or TS2
ordered sets with the Autonomous Change bit set.
Note that if the status bit is set by hardware in the same clock software
clears the status bit, the status bit should remain set and if MSI is
enabled, the hardware should trigger a new MSI.
14 RW1C 0
Link Bandwidth Management Status
This bit is set to 1 by hardware to indicate that either of the following has
occurred without the port transitioning through DL_Down status:
a) A link retraining initiated by a write of 1b to the Retrain Link bit has
completed
b) Hardware has autonomously changed link speed or width to attempt
to correct unreliable link operation
Note that if the status bit is set by hardware in the same clock software
clears the status bit, the status bit should remain set and if MSI is
enabled, the hardware should trigger a new MSI.
13 RO 0
Data Link Layer Link Active
This bit is set to 1 when the Data Link Control and Management State
Machine is in the DL_Active state, 0b otherwise.
On a downstream port or upstream port, when this bit is 0b, the
transaction layer associated with the link will abort all transactions that
would otherwise be routed to that link.
12 RWO 1
Slot Clock Configuration
This bit indicates whether Integrated I/O receives clock from the same
XTAL that also provides clock to the device on the other end of the link.
0 = Indicates that the device uses an independent clock irrespective of
the presence of a reference on the connector.
1 = Indicates the same physical reference clock to devices on both ends
of the link.
11 RO 0
Link Training
This field indicates the status of an ongoing link training session in the
PCI Express port
0 = LTSSM has exited the recovery/configuration state
1 = LTSSM is in recovery/configuration state or the Retrain Link was set
but training has not yet begun.
The Integrated I/O hardware clears this bit once LTSSM has exited the
recovery/configuration state. Refer to the latest PCI Express Base
Specification for details of which states within the LTSSM would set this
bit and which states would clear this bit.
10 RO 0 Reserved