Datasheet

Processor Integrated I/O (IIO) Configuration Registers
64 Datasheet, Volume 2
3.3.4.20 LNKCON—PCI Express* Link Control Register (Device 0)
The PCI Express Link Control register controls the PCI Express Link specific
parameters
.
Register: LNKCON
Device: 0 (DMI)
Function: 0
Offset: A0h
Bit Attr Default Description
15:12 RV 0 Reserved
11 RO 0
Link Autonomous Bandwidth Interrupt Enable
When set to 1, this bit enables the generation of an interrupt to indicate that
the Link Autonomous Bandwidth Status bit has been set.
10 RO 0
Link Bandwidth Management Interrupt Enable
When set to 1, this bit enables the generation of an interrupt to indicate that
the Link Bandwidth Management Status bit has been set.
9RO 0
Hardware Autonomous Width Disable
When set, this bit disables hardware from changing the link width for
reasons other than attempting to correct unreliable link operation
8RO 0
Enable Clock Power Management
N/A to Integrated I/O
7RO 0
Extended Sync
When set to 1, this bit forces the transmission of additional ordered sets
when exiting L0s and when in recovery. See the latest PCI Express Base
Specification for details.
6RO 0
Common Clock Configuration
Integrated I/O does nothing with this bit
5RO 0
Retrain Link
A write of 1 to this bit initiates link retraining in the given PCI Express port
by directing the LTSSM to the recovery state if the current state is [L0, L0s or
L1]. If the current state is anything other than L0, L0s, L1 then a write to
this bit does nothing. This bit always returns 0 when read.
If the Target Link Speed field has been set to a non-zero value different than
the current operating speed, then the LTSSM will attempt to negotiate to the
target link speed.
It is permitted to write 1b to this bit while simultaneously writing modified
values to other fields in this register. When this is done, all modified values
that affect link retraining must be applied in the subsequent retraining.
4RO 0
Link Disable
This field controls whether the link associated with the PCI Express port is
enabled or disabled. When this bit is a 1, a previously configured link (a link
that has gone past the polling state) would return to the “disabled” state as
defined in the PCI Express Base Specification. When this bit is clear, an
LTSSM in the “disabled” state goes back to the detect state.
0 = Enables the link associated with the PCI Express port.
1 = Disables the link associated with the PCI Express port.
3RO 0
Read Completion Boundary
Set to zero to indicate Integrated I/O could return read completions at 64B
boundaries.
2RV 0Reserved
1:0 RO 00
Active State Link PM Control
When 01b or 11b, L0s on transmitter is enabled, otherwise it is disabled.