Datasheet

Processor Integrated I/O (IIO) Configuration Registers
62 Datasheet, Volume 2
3.3.4.19 LNKCAP—PCI Express* Link Capabilities Register
The Link Capabilities register identifies the PCI Express specific link capabilities.
(Sheet 1 of 2)
Register: LNKCAP
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 9Ch
Bit Attr Default Description
31:24 RWO 0
Port Number
This field indicates the PCI Express port number for the link and is
initialized by software/BIOS.
23:22 RV 0h Reserved
21 RO 1
Link Bandwidth Notification Capability
A value of 1b indicates support for the Link Bandwidth Notification status
and interrupt mechanisms.
20 RO 1
Data Link Layer Link Active Reporting Capable
IIO supports reporting status of the data link layer so software knows
when it can enumerate a device on the link or otherwise know the status
of the link.
19 RO 1
Surprise Down Error Reporting Capable
IIO supports reporting a surprise down error condition
18 RO 0
Clock Power Management
Does not apply to IIO.
17:15 RWO 010
L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express port. It
indicates the length of time this port requires to complete transition from
L1 to L0.
000 = Less than 1 µs
001 = 1 is to less than 2 µs
010 = 2 is to less than 4 µs
011 = 4 is to less than 8 µs
100 = 8 is to less than 16 µs
101 = 16 is to less than 32 µs
110 = 32 is to 64 µs
111 = More than 64 µs
14:12 RWO 011
L0s Exit Latency
This field indicates the L0s exit latency (that is, L0s to L0) for the PCI
Express port.
000 = Less than 64 ns
001 = 64 ns to less than 128 ns
010 = 128 ns to less than 256 ns
011 = 256 ns to less than 512 ns
100 = 512 ns to less than 1 ns
101 = 1 is to less than 2 ns
110 = 2 is to 4 ns
111 = More than 4 ns
11:10 RWO 11
Active State Link PM Support
This field indicates the level of active state power management supported
on the given PCI Express port.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Supported