Datasheet

Processor Integrated I/O (IIO) Configuration Registers
60 Datasheet, Volume 2
1RW 0
Non Fatal Error Reporting Enable
Applies only to the PCI Express/DMI ports. Controls the reporting of non-fatal
errors that Integrated I/O detects on the PCI Express/DMI interface.
0 = Reporting of Non Fatal error detected by device is disabled.
1 = Reporting of Non Fatal error detected by device is enabled.
Refer to the latest PCI Express Base Specification for complete details of how
this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of
other internal component uncorrectable non-fatal errors (at the port unit) in
any way.
0RW 0
Correctable Error Reporting Enable
Applies only to the PCI Express/DMI ports. Controls the reporting of
correctable errors that Integrated I/O detects on the PCI Express/DMI
interface.
0 = Reporting of link Correctable error detected by the port is disabled.
1 = Reporting of link Correctable error detected by port is enabled.
Refer to the latest PCI Express Base Specification for complete details of how
this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of
other internal component correctable errors (at the port unit) in any way.
(Sheet 2 of 2)
Register: DEVCTRL
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 98h
Bit Attr Default Description