Datasheet

ManualsBrandsIntel Manualscomputer componentsBX8060515750

6 Datasheet, Volume 2

3.4.5.8 CWR[4:7]—Conditional Write Registers 4-7.................................130

3.4.5.9 CWR[8:11]—Conditional Write Registers 8-11.............................130

3.4.5.10 CWR[12:15]—Conditional Write Registers 12-15..........................130

3.4.5.11 CWR[16:17]—Conditional Write Registers 16-17..........................131

3.4.5.12 CWR[18:23]—Conditional Write Registers 18-23..........................131

3.4.5.13 IR[0:3]—Increment Registers 0-3..............................................131

3.4.5.14 IR[4:7]—Increment Registers 4-7..............................................132

3.4.5.15 IR[8:11]—Increment Registers 8-11..........................................132

3.4.5.16 IR[12:15]—Increment Registers 12-15.......................................132

3.4.5.17 IR[16:17]—Increment Registers 16-17.......................................133

3.4.5.18 IR[18:23]—Increment Registers 18-23.......................................133

3.4.6 System Control/Status Registers (Device 8, Function 2).............................134

3.4.6.1 SYSMAP—System Error Event Map Register ................................134

3.4.6.2 GENMCA—Generate MCA..........................................................134

3.4.6.3 SYRE—System Reset ...............................................................135

3.4.7 Miscellaneous Registers (Dev:8, F:3).......................................................135

3.4.7.1 IIOSLPSTS_L—IIO Sleep Status Low Register..............................135

3.4.7.2 IIOSLPSTS_H—IIO Sleep Status High Register ............................136

3.4.7.3 PMUSTATE—Power Management State Register...........................136

3.4.7.4 CTSTS—Throttling Status Register.............................................137

3.4.7.5 CTCTRL—Throttling Control Register ..........................................137

3.5 Intel

VT-d Memory Mapped Registers ...............................................................137

3.5.1 Intel

VT-d Configuration Register Space (MMIO) .....................................138

3.5.2 Register Description..............................................................................141

3.5.2.1 VTD_VERSION[0:1]—Version Number Register............................141

3.5.2.2 VTD_CAP[0:1]—Intel

VT-d Chipset Capabilities Register.............142

3.5.2.3 EXT_VTD_CAP[0:1]—Extended Intel

VT-d Capability Register......143

3.5.2.4 GLBCMD[0:1]—Global Command Register ..................................144

3.5.2.5 GLBSTS[0:1]—Global Status Register.........................................145

3.5.2.6 ROOTENTRYADD[0:1]—Root Entry Table Address Register............145

3.5.2.7 CTXCMD[0:1]—Context Command Register ................................146

3.5.2.8 FLTSTS[0:1]—Fault Status Register...........................................147

3.5.2.9 FLTEVTCTRL[0:1]—Fault Event Control Register ..........................148

3.5.2.10 FLTEVTDATA[0:1]—Fault Event Data Register .............................149

3.5.2.11 FLTEVTADDR[0:1]—Fault Event Address Register ........................149

3.5.2.12 FLTEVTUPRADDR[0:1]—Fault Event Upper Address Register..........149

3.5.2.13 PMEN[0:1]—Protected Memory Enable Register...........................149

3.5.2.14 PROT_LOW_MEM_BASE[0:1]—Protected Memory Low

Base Register .........................................................................150

3.5.2.15 PROT_LOW_MEM_LIMIT[0:1]—Protected Memory Low

Limit Register .........................................................................150

3.5.2.16 PROT_HIGH_MEM_BASE[0:1]—Protected Memory High

Base Register .........................................................................150

3.5.2.17 PROT_HIGH_MEM_LIMIT[0:1]—Protected Memory Limit

Base Register .........................................................................151

3.5.2.18 INV_QUEUE_HEAD[0:1]—Invalidation Queue Header

Pointer Register ......................................................................151

3.5.2.19 INV_QUEUE_TAIL[0:1]—Invalidation Queue Tail Pointer

3.5.2.20 INV_QUEUE_ADD[0:1]—Invalidation Queue Address

3.5.2.21 INV_COMP_STATUS[0:1]—Invalidation Completion Status

3.5.2.22 INV_COMP_EVT_CTL[0:1]—Invalidation Completion

Event Control Register .............................................................153

3.5.2.23 INV_COMP_EVT_DATA[0:1]—Invalidation Completion

Event Data Register.................................................................153

3.5.2.24 INV_COMP_EVT_ADDR[0:1]—Invalidation Completion

Event Address Register ............................................................153

3.5.2.25 INV_COMP_EVT_UPRADDR[0:1]—Invalidation Completion

Event Upper Address Register...................................................154