Datasheet

Datasheet, Volume 2 57

Processor Integrated I/O (IIO) Configuration Registers

3.3.4.15 PEGCAP—PCI Express* Capabilities Register

The PCI Express Capabilities register identifies the PCI Express device type and

associated capabilities.

Device: 0 (DMI), 3,5 (PCIe)

Function: 0

Offset: 92h

Bit Attr Default Description

15:14 RV 0h Reserved

13:9 RO 00h

Interrupt Message Number

Applies only to the root ports.

This field indicates the interrupt message number that is generated for

PM/HP events. When there are more than one MSI interrupt Number, this

Data and the MSI Message that is generated when the status bits in the slot

status register or root port status registers are set. IIO assigns the first

vector for PM/HP events and so this field is set to 0.

8RWO 0

Slot Implemented

Applies only to the root ports.

0 = Indicates no slot is connected to this port.

1 = Indicates that the PCI Express link associated with the port is connected

to a slot.

This register bit is of type “write once” and is controlled by BIOS/special

initialization firmware.

7:4 RO 0100

Device/Port Type

This field identifies the type of device. It is set to 0100 for all the Express

ports.

3:0 RWO

Dev 3,5: 2h

Dev 0: 1h

Capability Version

This field identifies the version of the PCI Express capability structure. Set to

2h for PCI Express devices for compliance with the extended base registers.

Note: BIOS should set this to 1h for Device 0 (DMI).