Datasheet

Processor Integrated I/O (IIO) Configuration Registers
56 Datasheet, Volume 2
3.3.4.12 MSIPENDING—MSI Pending Bit Register
The Mask Pending register enables software to defer message sending on a per-vector
basis.
3.3.4.13 PEGCAPID—PCI Express* Capability Identity Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
3.3.4.14 PEGNXTPTR—PCI Express* Next Pointer Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
Register: MSIPENDING
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 70h
Bit Attr Default Description
31:2 RV 0h Reserved
1:0 RO 0h
Pending Bit
For each Pending bit that is set, the PCI Express port has a pending associated
message.
Register: PEGCAPID
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 90h
Bit Attr Default Description
7:0 RO 10h Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
Register: PEGNXTPTR
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 91h
Bit Attr Default Description
7:0 RWO E0h
Next Ptr
This field is set to the PCI PM capability.