Datasheet

Datasheet, Volume 2 55

Processor Integrated I/O (IIO) Configuration Registers

3.3.4.10 MSIDR—MSI Data Register

The MSI Data Register contains all the data (interrupt vector) related to MSI interrupts

from the root ports.

3.3.4.11 MSIMSK—MSI Mask Bit Register

The Mask Bit register enables software to disable message sending on a per-vector

basis.

Device: 0 (DMI), 3,5 (PCIe)

Function: 0

Offset: 68h

Bit Attr Default Description

31:16 RO 0000h Reserved

15:14 RW 0h Reserved

13:12 RW 0h Reserved

11:8 RW 0h

Delivery Mode

0000 = Fixed: Trigger Mode can be edge or level.

0001 = Lowest Priority: Trigger Mode can be edge or level.

0010 = Intel SMI/PMI/MCA - Not supported using MSI of root port

0011 = Reserved - Not supported using MSI of root port

0100 = NMI - Not supported using MSI of root port

0101 = INIT - Not supported using MSI of root port

0110 = Reserved

0111 = ExtINT - Not supported using MSI of root port

1000–1111 - Reserved

7:0 RW 0h

Interrupt Vector

The interrupt vector (LSB) will be modified by the Integrated I/O to provide

context sensitive interrupt information for different events that require

attention from the processor, for example, Power Management and error

events.

Device: 0 (DMI), 3,5 (PCIe)

Function: 0

Offset: 6Ch

Bit Attr Default Description

31:2 RV 0h Reserved

1:0 RW 0h

Mask Bit

For each Mask bit that is set, the PCI Express* port is prohibited from sending

the associated message.