Datasheet
Datasheet, Volume 2 51
Processor Integrated I/O (IIO) Configuration Registers
3.3.4 Device-Specific PCI Configuration Space — 40h to FFh
3.3.4.1 SCAPID—Subsystem Capability Identity
3.3.4.2 SNXTPTR—Subsystem ID Next Pointer
2RW 0
ISA Enable
This bit modifies the response by the Integrated I/O to an I/O access issued by
the processor that target ISA I/O addresses. This applies only to I/O
addresses that are enabled by the IOBASE and IOLIM registers.
0 = All addresses defined by the IOBASE and IOLIM for processor I/O
transactions will be mapped to PCI Express.
1 = The Integrated I/O will not forward to PCI Express any I/O transactions
addressing the last 768 bytes in each 1-KB block even if the addresses
are within the range defined by the IOBASE and IOLIM registers.
1RW 0
SERR Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages from the PCI Express* port to the primary side.
0 = Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL.
1 = Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages.
0RW 0
Parity Error Response Enable
The Integrated I/O ignores this bit. This bit though affects the setting of Bit 8
in the SECSTS register.
Register: SCAPID
Device: 3,5 (PCIe)
Function: 0
Offset: 40h
Bit Attr Default Description
7:0 RO 0Dh
Capability ID
Assigned by PCI-SIG for subsystem capability ID.
Register:S NXTPTR
Device: 3,5 (PCIe)
Function: 0
Offset: 41h
Bit Attr Default Description
7:0 RWO 60h
Next Ptr
This field is set to 80h for the next capability list (MSI capability structure) in
the chain.
(Sheet 2 of 2)
Register: BCTRL
Device: 3,5 (PCIe)
Function: 0
Offset: 3Eh
Bit Attr Default Description