Datasheet
Processor Integrated I/O (IIO) Configuration Registers
48 Datasheet, Volume 2
3.3.3.23 PMBASE—Prefetchable Memory Base Register
The Prefetchable Memory Base and Memory Limit registers define a memory mapped
I/O prefetchable address range (64-bit addresses) which is used by the PCI Express
bridge to determine when to forward memory transactions based on the following
formula:
PREFETCH_MEMORY_BASE_UPPER::PREFETCH_MEMORY_BASE ≤ A[63:20] ≤
PREFETCH_MEMORY_LIMIT_UPPER::PREFETCH_MEMORY_LIMIT
The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers
are read/write and correspond to the upper 12 address bits, A[31:20] of the 32-bit
addresses. The bottom of the defined memory address range will be aligned to a 1-MB
boundary and the top of the defined memory address range will be one less than a
1-MB boundary
.
The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory
Limit registers are read-only, contain the same value, and encode whether or not the
bridge supports 64-bit addresses. If these four bits have the value 0h, then the bridge
supports only 32-bit addresses. If these four bits have the value 01h, then the bridge
supports 64-bit addresses and the Prefetchable Base Upper-32 bits and Prefetchable
Limit Upper 32-bits registers hold the rest of the 64-bit prefetchable base and limit
addresses respectively.
Setting the prefetchable memory limit less than prefetchable memory base disables the
64-bit prefetchable memory range altogether.
Note: In general, the memory base and limit registers won’t be programmed by software
without clearing the MSE bit first.
3.3.3.24 PMLIMIT—Prefetchable Memory Limit
Register: PMBASE
Device: 3,5 (PCIe)
Function: 0
Offset: 24h
Bit Attr Default Description
15:4 RW 000h
Prefetchable Memory Base Address
This field corresponds to A[31:20] of the prefetchable memory address on the
PCI Express* port.
3:0 RO 1h
Prefetchable Memory Base Address Capability
Integrated I/O sets this bit to 01h to indicate 64-bit capability.
Register: PMLIMIT
Device: 3,5 (PCIe)
Function: 0
Offset: 26h
Bit Attr Default Description
15:4 RW 000h
Prefetchable Memory Limit Address
This field corresponds to A[31:20] of the memory address on the PCI Express
bridge.
3:0 RO 1h
Prefetchable Memory Limit Address Capability
Integrated I/O sets this field to 01h to indicate 64-bit capability.