Datasheet

Datasheet, Volume 2 47
Processor Integrated I/O (IIO) Configuration Registers
3.3.3.21 MBAS—Memory Base
The Memory Base and Memory Limit registers define a memory-mapped I/O non-
prefetchable address range (32-bit addresses) and the Integrated I/O directs accesses
in this range to the PCI Express port based on the following formula:
MEMORY_BASE ≤ A[31:20] ≤ MEMORY_LIMIT
The upper 12 bits of both the Memory Base and Memory Limit registers are read/write
and corresponds to the upper 12 address bits, A[31:20] of 32-bit addresses. Thus, the
bottom of the defined memory address range will be aligned to a 1-MB boundary and
the top of the defined memory address range will be one less than a 1-MB boundary.
Setting the memory limit less than memory base disables the 32-bit memory range
altogether.
Note: In general, the memory base and limit registers will not be programmed by software
without clearing the MSE bit first.
3.3.3.22 MLIM—Memory Limit
Register: MBAS
Device: 3,5 (PCIe)
Function: 0
Offset: 20h
Bit Attr Default Description
15:4 RW 0h
Memory Base Address
This field corresponds to A[31:20] of the memory address on the PCI Express*
port.
3:0 RO 0h Reserved
Register: MLIM
Device: 3,5 (PCIe)
Function: 0
Offset: 22h
Bit Attr Default Description
15:4 RW 0h
Memory Limit Address
This field corresponds to A[31:20] of the memory address that corresponds to
the upper limit of the range of memory accesses that will be passed by the PCI
Express* bridge
3:0 RO 0h Reserved (by PCI-SIG)