Datasheet

Processor Integrated I/O (IIO) Configuration Registers
46 Datasheet, Volume 2
3.3.3.20 SECSTS—Secondary Status Register
Secondary Status register is a 16-bit status register that reports the occurrence of
various events associated with secondary side (that is, PCI Express/DMI side) of the
“virtual” PCI-to-PCI bridge.
Register: SECSTS
Device: 3,5 (PCIe)
Function: 0
Offset: 1Eh
Bit Attr Default Description
15 RW1C 0
Detected Parity Error
This bit is set by the Integrated I/O whenever it receives a poisoned TLP
in the PCI Express* port. This bit is set regardless of the state the Parity
Error Response Enable bit in the Bridge Control register.
14 RW1C 0
Received System Error
This bit is set by the Integrated I/O when it receives a ERR_FATAL or
ERR_NONFATAL message.
13 RW1C 0
Received Master Abort Status
This bit is set when the PCI Express port receives a Completion with
“Unsupported Request Completion” Status or when IIO master aborts a
Type 0 configuration packet that has a non-zero device number.
12 RW1C 0
Received Target Abort Status
This bit is set when the PCI Express port receives a Completion with
“Completer Abort” Status.
11 RW1C 0
Signaled Target Abort
This bit is set when the PCI Express port sends a completion packet with
a “Completer Abort” Status (including peer-to-peer completions that are
forwarded from one port to another).
10:9 RO 00
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8RW1C 0
Master Data Parity Error
This bit is set by the PCI Express port on the secondary side (PCI Express
link) if the Parity Error Response Enable bit (PERRE) is set in Bridge
Control register and either of the following two conditions occurs:
• The PCI Express port receives a Completion from PCI Express
marked poisoned.
• The PCI Express port poisons a packet with data.
If the Parity Error Response Enable bit in Bridge Control Register is
cleared, this bit is never set.
7RO 0
Fast Back-to-Back Transactions Capable
Not applicable to PCI Express. Hardwired to 0.
6RO 0Reserved
5RO 0
66-MHz Capability
Not applicable to PCI Express. Hardwired to 0.
4:0 RO 0h Reserved