Datasheet

Datasheet, Volume 2 45
Processor Integrated I/O (IIO) Configuration Registers
3.3.3.19 IOLIM—I/O Limit Register
The I/O Base register defines an address range that is used by the PCI Express port to
determine when to forward I/O transactions from one interface to the other using the
following formula:
IO_BASE ≤ A[15:12] ≤ IO_LIMIT
The bottom of the defined I/O address range will be aligned to a 4-KB (1-KB if EN1K bit
is set. Refer to IIOMISCCTRL register for definition of EN1K bit) boundary while the top
of the region specified by IO_LIMIT will be one less than a 4-KB (1-KB if EN1K bit is
set) multiple. Setting the I/O limit less than I/O base disables the I/O range altogether.
Note: In general, the I/O limit register will not be programmed by software without clearing
the IOSE bit first.
Register: IOLIM
Device: 3,5 (PCIe)
Function: 0
Offset: 1Dh
Bit Attr Default Description
7:4 RW 0h
I/O Address Limit
Corresponds to A[15:12] of the I/O addresses at the PCI Express* port.
3:2 RWL 0h
When EN1K is set, these bits become RW and allow for 1-K granularity of
I/O addressing, otherwise these bits are RO.
1:0 RO 0h
I/O Address Limit Capability
IIO only supports 16-bit addressing.