Datasheet
Processor Integrated I/O (IIO) Configuration Registers
44 Datasheet, Volume 2
3.3.3.17 SUBBUS—Subordinate Bus Number Register
This register identifies the subordinate bus (if any) that resides at the level below the
secondary bus of the PCI Express interface. This number is programmed by the PCI
configuration software to allow mapping of configuration cycles to devices subordinate
to the secondary PCI Express port.
3.3.3.18 IOBAS—I/O Base Register
The I/O Base register defines an address range that is used by the PCI Express port to
determine when to forward I/O transactions from one interface to the other using the
following formula:
IO_BASE ≤ A[15:12] ≤ IO_LIMIT
The bottom of the defined I/O address range will be aligned to a 4-KB (1-KB if EN1K bit
is set. Refer to the IIOMISCCTRL register for the definition of EN1K bit) boundary while
the top of the region specified by IO_LIMIT will be one less than a 4-KB (1-KB if EN1K
bit is set) multiple. Setting the I/O limit less than I/O base disables the I/O range
altogether.
Note: In general, the I/O base register will not be programmed by software without clearing
the IOSE bit first.
Register: SUBBUS
Device: 3,5 (PCIe)
Function: 0
Offset: 1Ah
Bit Attr Default Description
7:0 RW 00h
Subordinate Bus Number
This register is programmed by configuration software with the number
of the highest subordinate bus that is behind the PCI Express* port. Any
transaction that falls between the secondary and subordinate bus
number (both inclusive) of an Express port is forwarded to the express
port.
Register: IOBAS
Device: 3,5 (PCIe)
Function: 0
Offset: 1Ch
Bit Attr Default Description
7:4 RW 0h
I/O Base Address
Corresponds to A[15:12] of the I/O addresses at the PCI Express* port.
3:2 RWL 0h
When EN1K is set (Refer to IIOMISCCTRL register for definition of EN1K
bit), these bits become RW and allow for 1-K granularity of I/O
addressing; otherwise, these are RO.
1:0 RO 0h
I/O Address Capability
Integrated I/O supports only 16-bit addressing