Datasheet

Datasheet, Volume 2 43
Processor Integrated I/O (IIO) Configuration Registers
3.3.3.14 INTPIN—Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC, and INTD as
determined by BIOS/firmware.
3.3.3.15 PBUS—Primary Bus Number Register
This register identifies the bus number on the on the primary side of the PCI Express
port.
3.3.3.16 SECBUS—Secondary Bus Number
This register identifies the bus number assigned to the secondary side (PCI Express) of
the “virtual” PCI-to-PCI bridge. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices connected to PCI Express.
Register: INTPIN
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 3Dh
Bit Attr Default Description
7:0 RWO 01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express
port.
001 = Generate INTA
010 = Generate INTB
011 = Generate INTC
100 = Generate INTD
Others = Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
Register: PBUS
Device: 3,5 (PCIe)
Function: 0
Offset: 18h
Bit Attr Default Description
7:0 RW 00h
Primary Bus Number
Configuration software programs this field with the number of the bus on
the primary side of the bridge. BIOS must program this register to the
correct value since Integrated I/O hardware would depend on this
register for inbound decode purposes.
Register: SECBUS
Device: 3,5 (PCIe)
Function: 0
Offset: 19h
Bit Attr Default Description
7:0 RW 00h
Secondary Bus Number
This field is programmed by configuration software to assign a bus
number to the secondary bus of the virtual PCI-to-PCI bridge.