Datasheet

Datasheet, Volume 2 41
Processor Integrated I/O (IIO) Configuration Registers
3.3.3.7 CLSR—Cacheline Size Register
3.3.3.8 PLAT—Primary Latency Timer
The above register denotes the maximum time slice for a burst transaction in legacy
PCI 2.3 on the primary interface. It does not affect/influence PCI Express functionality.
3.3.3.9 HDR—Header Type Register
This register identifies the header layout of the configuration space.
Register: CLSR
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 0Ch
Bit Attr Default Description
7:0 RW 0h
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size
for Integrated I/O is always 64B. Hardware ignores this setting.
Register: PLAT
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 0Dh
Bit Attr Default Description
7:0 RO 00h
Prim_Lat_timer: Primary Latency Timer
Not applicable to PCI Express*. Hardwired to 00h.
Register: HDR
Device: 0 (DMI)
Function: 0
Offset: 0Eh
Bit Attr Default Description
7RO0
Multi-Function Device
This bit defaults to 0 for PCI Express*/DMI ports.
6:0 RO 00h
Configuration Layout
This field identifies the format of the configuration header layout.
For Device 0 (DMI), default is 00h indicating a conventional type 00h PCI
header.
Register: HDR
Device: 3,5 (PCIe)
Function: 0
Offset: 0Eh
Bit Attr Default Description
7RO0
Multi-Function Device
This bit defaults to 0 for PCI Express*/DMI ports.
6:0 RO 01h
Configuration Layout
This field identifies the format of the configuration header layout. It is Type 1
for all PCI Express ports.
The default is 01h, indicating a PCI-to-PCI bridge.