Datasheet

Processor Integrated I/O (IIO) Configuration Registers
40 Datasheet, Volume 2
3.3.3.5 RID—Revision Identification Register
This register contains the revision number of the Integrated I/O.
3.3.3.6 CCR—Class Code Register
This register contains the Class Code for the device.
Register: RID
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 08h
Bit Attr Default Description
7:4 RWO
See
Description
Minor Revision
Steppings that required all masks be regenerated. Refer to the Intel
®
Core™ i7-800 and i5-700 Desktop Processor Series Speci
fication Update
for the value of the Revision ID Register.
3:0 RWO
See
Description
Minor Revision Identification Number
Increment for each steppings that do not require masks to be
regenerated. Refer to the Intel
®
Core™ i7-800 and i5-700 Desktop
Processor Series Speci
fication Update for the value of the Revision
ID Register.
Register: CCR
Device: 0
Function: 0
Offset: 09h
Bit Attr Default Description
23:16 RO 06h
Base Class
For DMI port, this field is hardwired to 06h, indicating it is a “Bridge Device.”
15:8 RO 00h
Sub-Class
For Device 0 (DMI), this field defaults to 00h to indicate a “Host Bridge.”
7:0 RO 00h
Register-Level Programming Interface
This field is hardwired to 00h for DMI port.
Register: CCR
Device: 3,5 (PCIe)
Function: 0
Offset: 09h
Bit Attr Default Description
23:16 RO 06h
Base Class
For PCI Express ports this field is hardwired to 06h, indicating it is a
“Bridge Device.”
15:8 RO
See
Description
Sub-Class
For PCI Express ports, this field defaults to 04h indicating “PCI-to-PCI
bridge”. This register changes to the sub class of 00h to indicate “Host
Bridge,” when bit 0 in “MISCCTRLSTS—Misc Control and Status Register”
is set.
7:0 RO 00h
Register-Level Programming Interface
This field is hardwired to 00h for PCI Express ports.