Datasheet

Datasheet, Volume 2 39
Processor Integrated I/O (IIO) Configuration Registers
13 RW1C 0
Received Master Abort Status
This bit is set when a device experiences a master abort condition on a
transaction it mastered on the primary interface (Integrated I/O internal
bus). Note that certain errors might be detected right at the PCI Express
interface and those transactions might not “propagate” to the primary
interface before the error is detected (for example, accesses to memory
above TOCM in cases where the PCI Express* interface logic itself might
have visibility into TOCM). Such errors do not cause this bit to be set,
and are reported using the PCI Express interface error bits (secondary
status register). Conditions that cause Bit 13 to be set, include:
• Device receives a completion on the primary interface (internal bus
of Integrated I/O) with Unsupported Request or master abort
completion Status. This includes UR status received on the primary
side of a PCI Express port on peer-to-peer completions also.
• Device accesses to holes in the main memory address region that
are detected by Intel QuickPath Interconnect Source Address
Decoder.
• Other master abort conditions detected on the Integrated I/O
internal bus.
12 RW1C 0
Received Target Abort
This bit is set when a device experiences a completor abort condition on
a transaction it mastered on the primary interface (Integrated I/O
internal bus). Note that certain errors might be detected right at the PCI
Express interface and those transactions might not propagate to the
primary interface before the error is detected (for example, accesses to
memory above VTCSRBASE). Such errors do not cause this bit to be set,
and are reported using the PCI Express interface error bits (secondary
status register). Conditions that cause Bit 12 to be set, include:
• Device receives a completion on the primary interface (internal bus
of Integrated I/O) with completor abort completion Status. This
includes CA status received on the primary side of a PCI Express port
on peer-to-peer completions also.
• Accesses to Intel QuickPath Interconnect that return a failed
completion status.
• Other completer abort conditions detected on the Integrated
I/O internal bus.
11 RW1C 0
Signaled Target Abort
This bit is set when a device signals a completer abort completion status
on the primary side (internal bus of Integrated I/O). This condition
includes a PCI Express port forwarding a completer abort status received
on a completion from the secondary side and passed to the primary side
on a peer-to-peer completion.
10:9 RO 0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8 RW1C 0
Master Data Parity Error
This bit is set by a device if the Parity Error Response bit in the PCI
Command register is set and it receives a completion with poisoned data
from the primary side or if it forwards a packet with data (including MSI
writes) to the primary side with poison.
7RO 0
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
6RO 0Reserved
5RO 0
66-MHz Capable
Not applicable to PCI Express. Hardwired to 0.
4RO 1
Capabilities List
This bit indicates the presence of a capabilities list structure.
3RO 0Reserved
2:0 RO 0h Reserved
(Sheet 2 of 2)
Register: PCISTS
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 06h
Bit Attr Default Description