Datasheet
Processor Integrated I/O (IIO) Configuration Registers
38 Datasheet, Volume 2
3.3.3.4 PCISTS—PCI Status Register
The PCI Status register is a 16-bit status register that reports the occurrence of various
events associated with the primary side of the “virtual” PCI-to-PCI bridge embedded in
PCI Express ports and also primary side of the other devices on the internal Processor
Integrated I/O bus.
1RW 0
Memory Space Enable (MSE)
0 = Disables a PCI Express port’s memory range registers (including the
CSR range registers) to be decoded as valid target addresses for
transactions from primary side.
1 = Enables a PCI Express port’s memory range registers to be decoded
as valid target addresses for transactions from primary side.
Note that if a PCI Express port’s MSE bit is clear, that port can still be
target of any memory transaction if subtractive decoding is enabled on
that port.
0RW 0
IO Space Enable (IOSE)
Applies to PCI Express ports
0 = Disables the I/O address range, defined in the IOBASE and IOLIM
registers of the PCI-to-PCI bridge header, for target decode from
primary side.
1 = Enables the I/O address range, defined in the IOBASE and IOLIM
registers of the PCI-to-PCI bridge header, for target decode from
primary side.
Note that if a PCI Express port’s IOSE bit is clear, that port can still be
target of an I/O transaction if subtractive decoding is enabled on that
port.
(Sheet 2 of 2)
Register: PCICMD
Device: 3,5 (PCIe*)
Function: 0
Offset: 04h
Bit Attr Default Description
(Sheet 1 of 2)
Register: PCISTS
Device: 0 (DMI), 3,5 (PCIe)
Function: 0
Offset: 06h
Bit Attr Default Description
15 RW1C 0
Detected Parity Error
This bit is set by a device when it receives a packet on the primary side
with an uncorrectable data error or an uncorrectable address/control
parity error. The setting of this bit is regardless of the Parity Error
Response bit (PERRE) in the PCICMD register.
14 RW1C 0
Signaled System Error
0 = The device did not report a fatal/non-fatal error.
1 = The device reported fatal/non-fatal (and not correctable) errors it
detected on its PCI Express* interface through a message to the
PCH, with SERRE bit enabled. Software clears this bit by writing a 1
to it. For PCI Express ports, this bit is also set (when SERR enable
bit is set) when a FATAL/NON-FATAL message is forwarded from the
Express link to the PCH using a message.