Datasheet

Datasheet, Volume 2 31
Processor Integrated I/O (IIO) Configuration Registers
Table 3-2. Device 0 (DMI) Configuration Map
DID VID 00h 80h
PCISTS PCICMD 04h
84h
CCR RID 08h
88h
HDR PLAT CLSR 0Ch
8Ch
10h PEGCAP PEGNXTPTR PEGCAPID 90h
14h DEVCAP 94h
18h DEVSTS DEVCTRL 98h
1Ch LNKCAP 9Ch
20h LNKSTS LNKCON A0h
24h A4h
28h A8h
SID SVID 2Ch ROOTCAP ROOTCON ACh
30h ROOTSTS B0h
CAPPTR 34h DEVCAP2 B4h
38h DEVCTRL2 B8h
INTPIN INTLIN 3Ch BCh
40h LNKCON2 C0h
44h C4h
48h C8h
4Ch CCh
DMIRCBAR 50h
D0h
54h D4h
58h D8h
5Ch DCh
MSICTL MSINXTPTR MSICAPID 60h PMCAP E0h
MSIAR 64h PMCSR E4h
MSIDR 68h E8h
MSIMSK 6Ch
ECh
MSIPENDING 70h
F0h
74h F4h
78h F8h
7Ch FCh