Datasheet

Datasheet, Volume 2 29
Processor Integrated I/O (IIO) Configuration Registers
treated as static in the sense that they will not be changed without the decode control
bits being clear. Registers outside of this standard space will be noted as dynamic when
appropriate.
3.3.2 Configuration Register Map
Figure 3-1. DMI Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space
00h
40h
100h
FFFh
M S I C a p a bility
P2P'
CAP_PTR
P C IE C a p a b ility
Extended
Configuration Space
PCI Device
Dependent
PCI Header
P M C a p ability
SVID/SDID Capability