Datasheet

Datasheet, Volume 2 255
Processor Uncore Configuration Registers
4.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS
MC_CHANNEL_1_SCHEDULER_PARAMS
These are the parameters used to control parameters within the scheduler.
4.10.25 MC_CHANNEL_0_MAINTENANCE_OPS
MC_CHANNEL_1_MAINTENANCE_OPS
This register enables various maintenance operations such as Refreshes, ZQ, RCOMP,
and so forth.
Device: 4, 5
Function: 0
Offset: B8h
Access as a DWord
Bit Attr Default Description
31:14 RO 0 Reserved
13 RW 0
DDR_CLK_TRISTATE_DISABLE. When set to 0, DDR clock drivers will
always be enabled.
12 RW 0
CS_ODT_TRISTATE_DISABLE. When set to 0, CS and ODT drivers will
always be enabled.
11 RW 0
FLOAT_EN
When set to 1, the address and command lines will float to save power
when commands are not being sent out.
10:6 RW 7
PRECASRDTHRESHOLD
Threshold above which Medium-Low Priority reads can PRE-CAS write
requests.
5RW 0
DISABLE_ISOC_RBC_RESERVE
When set to 1, this bit will prevent any RBC's from being reserved for
ISOC.
4RW 0ENABLE3N. Enable 3n Timing
3RW 0ENABLE2N. Enable 2n Timing
2:0 RW 0
PRIORITYCOUNTER
Upper 3 MSB of 8-bit priority time out counter.
Device: 4, 5
Function: 0
Offset: BCh
Access as a DWord
Bit Attr Default Description
31:13 RO 0 Reserved
12:0 RW 0
MAINT_CNTR
Value to be loaded in the maintenance counter. This counter sequences the
rate to Refreshes, ZQ, RCOMP. It should be set to 7800/DCLKperiodInNS. The
value of 0 is invalid.