Datasheet

Processor Uncore Configuration Registers
252 Datasheet, Volume 2
4.10.18 MC_CHANNEL_0_ODT_PARAMS2
MC_CHANNEL_1_ODT_PARAMS2
This register contains parameters that specify Forcing ODT on Specific ranks.
4.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD
MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD
This register contains the ODT activation matrix for RANKS 0 to 3 for Reads.
Device: 4, 5
Function: 0
Offset: A0h
Access as a DWord
Bit Attr Default Description
31:10 RO 0 Reserved
9RW 0MCODT_Writes. Drive MC ODT on reads and writes.
8RW 0FORCE_MCODT. Force MC ODT to always be asserted.
7RW 0FORCE_ODT7. Force ODT for Rank 7 to always be asserted.
6RW 0FORCE_ODT6. Force ODT for Rank 6 to always be asserted.
5RW 0FORCE_ODT5. Force ODT for Rank 5 to always be asserted.
4RW 0FORCE_ODT4. Force ODT for Rank 4 to always be asserted.
3RW 0FORCE_ODT3. Force ODT for Rank 3 to always be asserted.
2RW 0FORCE_ODT2. Force ODT for Rank 2 to always be asserted.
1RW 0FORCE_ODT1. Force ODT for Rank 1 to always be asserted.
0RW 0FORCE_ODT0. Force ODT for Rank 0 to always be asserted.
Device: 4, 5
Function: 0
Offset: A4h
Access as a DWord
Bit Attr Default Description
31:24 RW 1 ODT_RD3. ODT values for all 8 Ranks when reading Rank 3.
23:16 RW 1 ODT_RD2. ODT values for all 8 Ranks when reading Rank 2.
15:8 RW 4 ODT_RD1. ODT values for all 8 Ranks when reading Rank 1.
7:0 RW 4 ODT_RD0. ODT values for all 8 Ranks when reading Rank 0.