Datasheet

Datasheet, Volume 2 251
Processor Uncore Configuration Registers
4.10.17 MC_CHANNEL_0_ODT_PARAMS1
MC_CHANNEL_1_ODT_PARAMS1
This register contains parameters that specify ODT timings. All values are in DCLK.
Device: 4, 5
Function: 0
Offset: 9Ch
Access as a DWord
Bit Attr Default Description
31:27 RO 0 Reserved
26:24 RW 0
TAOFD
ODT turn off delay.
23:20 RW 6
MCODT_DURATION
Controls the duration of MC ODT activation. BL/2 + 2.
19:16 RW 4
MCODT_DELAY
Controls the delay from Rd CAS to MC ODT activation. This value is tCAS–1.
15:12 RW 5
ODT_RD_DURATION
Controls the duration of Rd ODT activation. This value is BL/2 + 2.
11:8 RW 0
ODT_RD_DELAY
Controls the delay from Rd CAS to ODT activation. This value is tCAS–tWL.
7:4 RW 5
ODT_WR_DURATION
Controls the duration of Wr ODT activation. value is BL/2 + 2.
3:0 RW 0
ODT_WR_DELAY
Controls the delay from Wr CAS to ODT activation. This value is always 0.