Datasheet
Datasheet, Volume 2 237
Processor Uncore Configuration Registers
4.10 Integrated Memory Controller Channel Control
Registers
4.10.1 MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD
Integrated Memory Controller DIMM reset command register. This register is used to
sequence the reset signals to the DIMMs.
Device: 4, 5
Function: 0
Offset: 50h
Access as a DWord
Bit Attr Default Description
31:3 RO 0 Reserved
2RW 0
BLOCK_CKE
When set, CKE will be forced to be deasserted.
1RW 0
ASSERT_RESET
When set, Reset will be driven to the DIMMs.
0WO 0
RESET
Reset the DIMMs. Setting this bit will cause the Integrated Memory
Controller DIMM Reset state machine to sequence through the reset
sequence using the parameters in MC_DIMM_INIT_PARAMS.