Datasheet
Processor Uncore Configuration Registers
232 Datasheet, Volume 2
4.9.3 MC_DIMM_CLK_RATIO
Requested DIMM clock ratio (Qclk). This is the data rate going to the DIMM. The clock
sent to the DIMM is 1/2 of QCLK rate.
4.9.4 MC_TEST_LTRCON
Memory test configuration register.
Device: 3
Function: 4
Offset: 54h
Access as a DWord
Bit Attr Default Description
31:5 RO 0 Reserved
4:0 RW 6
QCLK_RATIO
Requested ratio of Qclk/Bclk.
00000 = RSVD
00010 = 266 MHz
00100 = 533 MHz
00110 = 800 MHz
01000 = 1066 MHz
01010 = 1333 MHz
Device: 3
Function: 4
Offset: 5Ch
Access as a DWord
Bit Attr Default Description
31:27 RO 0 Reserved
26:25 RW 0
Link_Select
Selects DDR channel.
00 = Channel 0
01 = Channel 1
10 = Reserved
11 = Global Scan Chain
24:5 RO 0 Reserved
4:0 RW 0 Link_Control