Datasheet

Processor Uncore Configuration Registers
222 Datasheet, Volume 2
4.7.4 MC_STATUS
MC Primary Status register.
4.7.5 MC_RESET_CONTROL
DIMM Reset enabling controls.
Device: 3
Function: 0
Offset: 4Ch
Access as a DWord
Bit Attr Default Description
31:17 RO 0 Reserved
4RO 1Reserved
3RO 0Reserved
2RO 0Reserved
1RO 0
CHANNEL1_DISABLED. Channel 1 is disabled.
This can be factory configured or if Init done is written without the
channel_active being set. Clocks in the channel will be disabled when this bit
is set.
0RO 0
CHANNEL0_DISABLED. Channel 0 is disabled.
This can be factory configured or if Init done is written without the
channel_active being set. Clocks in the channel will be disabled when this bit
is set.
Device: 3
Function: 0
Offset: 5Ch
Access as a DWord
Bit Attr Default Description
31:1 RO 0 Reserved
0WO 0
BIOS_RESET_ENABLE
When set, MC takes over control of driving RESET to the DIMMs. This bit is
set on S3 exit and cold boot to take over RESET driving responsibility from
the physical layer.