Datasheet

Datasheet, Volume 2 215
Processor Uncore Configuration Registers
4.5.9 SAD_MESEG_BASE
Register for Intel Management Engine (Intel ME) range base address.
4.5.10 SAD_MESEG_MASK
Register for Intel ME mask.
Device: 0
Function: 1
Offset: 70h
Access as a QWord
Bit Attr Default Description
63:40 RV 0 Reserved
39:19 RW 0
BASE ADDRESS
Base address of Intel ME SEG. Must be 4-K aligned (space must be power of
2 aligned).
18:0 RO 0 Reserved
Device: 0
Function: 1
Offset: 78h
Access as a QWord
Bit Attr Default Description
63:40 RV 0 Reserved
39:19 RW 0
MASK
Mask of Intel ME SEG. Space must be power of 2 aligned. Field indicates
which bits must match the BASE in order to be inside the Intel ME range.
11 RW 0
ENABLE
Enable for Intel ME SEG. When enabled, all core access to Intel ME SEG
space is aborted.
10 RWL 0
LOCK
Lock for Intel ME SEG base and mask.
9:0 RO 0 Reserved