Datasheet

Processor Uncore Configuration Registers
214 Datasheet, Volume 2
4.5.7 SAD_MCSEG_BASE
Global register for McSEG address space. These are designed to look just like the cores
SMRR type registers.
4.5.8 SAD_MCSEG_MASK
Global register for McSEG address space. These are designed to look just like the cores
SMRR type registers.
Device: 0
Function: 1
Offset: 60h
Access as a QWord
Bit Type Default Description
63:40 RV 0 Reserved
39:19 RW 0
BASE_ADDRESS
Base address of McSEG. Must be 4K aligned (space must be power of 2
aligned).
18:0 RO 0 Reserved
Device: 0
Function: 1
Offset: 68h
Access as a QWord
Bit Type Default Description
63:40 RV 0 Reserved
39:19 RW 0
MASK
Mask of McSEG. Space must be power of 2 aligned.
18:12 RO 0 Reserved
11 RW 0
ENABLE
Is McSeg Enabled.
10 RW 0
LOCK
Is McSeg/Mask register locked.
9:0 RO 0 Reserved