Datasheet

Processor Uncore Configuration Registers
190 Datasheet, Volume 2
Table 4-7. Device 3, Function 1 — Target Address Decoder Registers
DID VID 00h TAD_DRAM_RULE_0 80h
PCISTS PCICMD 04h TAD_DRAM_RULE_1 84h
CCR RID 08h TAD_DRAM_RULE_2 88h
HDR 0Ch TAD_DRAM_RULE_3 8Ch
10h TAD_DRAM_RULE_4 90h
14h TAD_DRAM_RULE_5 94h
18h TAD_DRAM_RULE_6 98h
1Ch TAD_DRAM_RULE_7 9Ch
20h A0h
24h A4h
28h A8h
SID SVID 2Ch
ACh
30h B0h
34h B4h
38h B8h
3Ch BCh
40h TAD_INTERLEAVE_LIST_0 C0h
44h TAD_INTERLEAVE_LIST_1 C4h
48h TAD_INTERLEAVE_LIST_2 C8h
4Ch TAD_INTERLEAVE_LIST_3 CCh
50h TAD_INTERLEAVE_LIST_4 D0h
54h TAD_INTERLEAVE_LIST_5 D4h
58h TAD_INTERLEAVE_LIST_6 D8h
5Ch TAD_INTERLEAVE_LIST_7 DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
7Ch FCh