Datasheet

Datasheet, Volume 2 177

Processor Integrated I/O (IIO) Configuration Registers

3.7.1 Intel

QuickPath Interconnect Link Layer Registers

The link layer register are defined for the coherent link. There is a special attribute on

some link layer registers to handle the link layer specific reset. The link layer only has

hard and soft resets. ‘N’ attribute indicates that the register is reset on a link layer hard

reset. ‘NN’ indicates that the register is reset on any link layer reset (hard or soft).

3.7.1.1 SVID—Subsystem Vendor ID

3.7.1.2 SID—Subsystem Device ID

3.7.1.3 CAPPTR—Capability Pointer

The CAPPTR provides the offset to the location of the first device capability in the

capability list.

Device: 16

Function: 0,1

Offset: 2Ch

Bit Attr Default Description

7:0 RWO 00h

Subsystem Vendor Identification

This field is programmed during boot-up to indicate the vendor of the system

board. After it has been written once, it becomes read only.

Device: 16

Function: 0,1

Offset: 2Eh

Bit Attr Default Description

7:0 RWO 00h

Subsystem Identification Number

Assigned by the subsystem vendor to uniquely identify the subsystem.

Device: 16

Function: 0,1

Offset: 34h

Bit Attr Default Description

7:0 RO 00h: F 0/1 Capability Pointer Points to the first capability structure for the device.