Datasheet

Processor Integrated I/O (IIO) Configuration Registers
172 Datasheet, Volume 2
3.6.1.17 TXT.MSEG.BASE—Intel
®
TXT MSEG Base Register
This register holds a pointer to the base address for the TXT MSEG.
General Behavioral Rules:
• This is a read/write register.
• This register is locked by TXT.CMD.LOCK.BASE. When locked it may not be changed
by any writes, whether they are Intel TXT private or public writes.
• This register is available for read or write in the Public Intel TXT configuration
space.
• This register is available for read or write in the Private Intel TXT configuration
space.
3.6.1.18 TXT.MSEG.SIZE—Intel
®
TXT MSEG Size Register
This register holds the size (in bytes) of the Intel TXT MSEG region.
General Behavioral Rules:
• This is a read/write register.
• This register is locked by TXT.CMD.LOCK.BASE. When locked it may not be changed
by any writes, whether they are Intel TXT private or public writes.
• This register is available for read or write in the Public Intel TXT configuration
space.
• This register is available for read or write in the Private Intel TXT configuration
space.
Base: TXT_TXT Offset: 0310h
Base: TXT_PR Offset: 0310h
Base: TXT_PB Offset: 0310h
Bit Attr Default Description
63:0 RWL 0h
TXT.MSEG.BASE[63:0]
This register will be locked for access using Intel TXT public space when the
TXT.CMD.LOCK.BASE is issued. When locked this register is updated by
private or Intel TXT writes, but not public writes.
Base: TXT_TXT Offset: 0318h
Base: TXT_PR Offset: 0318h
Base: TXT_PB Offset: 0318h
Bit Attr Default Description
63:0 RWL 0h
TXT.MSEG.SIZE[63:0]
This register will be locked for access using Intel TXT public space when the
TXT.CMD.LOCK.BASE is issued. When locked this register is updated by
private or Intel TXT writes, but not public writes.