Datasheet

Datasheet, Volume 2 171
Processor Integrated I/O (IIO) Configuration Registers
3.6.1.15 TXT.HEAP.BASE—Intel
®
TXT HEAP Code Base Register
This register holds a pointer to the base address for the Intel TXT Heap.
General Behavioral Rules:
• This is a read/write register.
• This register is locked by TXT.CMD.LOCK.BASE. When locked this register is
updated by private or Intel TXT writes, but not public writes
• This register is available for read or write in the Public Intel TXT configuration
space.
• This register is available for read or write in the Private Intel TXT configuration
space.
3.6.1.16 TXT.HEAP.SIZE—Intel
®
TXT HEAP Size Register
This register indicates the size of the Intel TXT Heap.
General Behavioral Rules:
• This is a read/write register.
• This register is locked by TXT.CMD.LOCK.BASE. When locked this register is
updated by private or Intel TXT writes, but not public writes
• This register is available for read or write in the Public Intel TXT configuration
space.
• This register is available for read or write in the Private Intel TXT configuration
space.
Base: TXT_TXT Offset: 0300h
Base: TXT_PR Offset: 0300h
Base: TXT_PB Offset: 0300h
Bit Attr Default Description
63:0 RWLB 0h
TXT.HEAP.BASE[63:0]
Base address of the heap.
This register will be locked for access using Intel TXT public space when the
TXT.CMD.LOCK.BASE is issued. When locked this register is updated by
private or Intel TXT writes, but not public writes.
Base: TXT_TXT Offset: 0308h
Base: TXT_PR Offset: 0308h
Base: TXT_PB Offset: 0308h
Bit Attr Default Description
63:0 RWLB 0h
TXT.HEAP.SIZE[63:0]
Size of the total device space in bytes.
This register will be locked for access using Intel TXT public space when the
TXT.CMD.LOCK.BASE is issued. When locked this register is updated by
private or Intel TXT writes, but not public writes.