Datasheet

Datasheet, Volume 2 169
Processor Integrated I/O (IIO) Configuration Registers
3.6.1.11 TXT.CMD.UNLOCK.BASE—Intel
®
TXT Unlock Base Command
Register
When this command is invoked, the chipset unlocks the registers listed in the table of
registers and commands. When unlocked, the registers affected by this command may
be written with public cycles, as well as private or Intel TXT cycles.
General Behavioral Rules:
• This is a write-only register.
• This register is only available in the Private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
meaning.
3.6.1.12 TXT.SINIT.MEMORY.BASE—Intel
®
TXT SINIT Code Base Register
This register holds a pointer to the base address of the SINIT code.
General Behavioral Rules:
• This is a read/write register.
• This register is available for reads or writes in the Public Intel TXT configuration
space.
• This register is available for read or write in the Private Intel TXT configuration
space.
Base: TXT_TXT Offset: 0238h
Base: TXT_PR Offset: 0238h
Bit Attr Default Description
7:0 WO 0h N/A
Base: TXT_TXT Offset: 0270h
Base: TXT_PR Offset: 0270h
Base: TXT_PB Offset: 0270h
Bit Attr Default Description
63:40 RO 0h Reserved
39:12 RW 0h
TXT.SINIT.BASE[39:12]
Base address of the SINIT code.
Note: Only Bits 39:12 are implemented because the SINIT code must be
aligned to a 4-KB page boundary.
11:0 RO 0h Reserved