Datasheet
Processor Integrated I/O (IIO) Configuration Registers
168 Datasheet, Volume 2
3.6.1.9 TXT.ID—Intel
®
TXT Identifier Register
This register holds TXT ID for IIO.
General Behavioral Rules:
• This register is available in both the Public and Private Intel TXT configuration
spaces.
Note: Intel Chipset Implementation Notes: For IIO, the TXT.MIF.LARGE.CAP bit will be 1. IIO
will support having any pointers point to addresses above 4G.
3.6.1.10 TXT.CMD.LOCK.BASE—Intel
®
TXT Lock Base Command Register
When this command is invoked, the chipset will lock the registers listed in the table of
registers and commands. The command may be used by SCHECK or by SINIT to lock
down the location of code or any other information that needs to be passed between
SCHECK and the VMM and its loader.
General Behavioral Rules:
• This is a write-only register.
• This register is only available in the Private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
meaning.
Base: TXT_TXT Offset: 0110h
Base: TXT_PR Offset: 0110h
Base: TXT_PB Offset: 0110h
Bit Attr Default Description
63:48 RWLBS 0h
TXT.ID.EXT
This is an Extension onto the other ID fields.
This register will be locked for access using Intel TXT public space when
the TXT.CMD.LOCK.BASE is issued. When locked this register is updated
by private or Intel TXT writes, but not public writes.
47:32 RO 0h
TXT.RID
Revision ID
This field is revision dependent.
Refer to the Intel
®
Core™ i7-800 and i5-700 Desktop Processor Series
Speci
fication Update for the value of the Revision ID Register.
31:16 RO C002h TXT.DID - Device ID C002h
15:0 RO 8086h
TXT.VID
Vendor ID = 8086 for Intel corporation.
Base: TXT_TXT Offset: 0230h
Base: TXT_PR Offset: 0230h
Bit Attr Default Description
7:0 WO 0h N/A