Datasheet

Datasheet, Volume 2 167
Processor Integrated I/O (IIO) Configuration Registers
3.6.1.7 TXT.CMD.CLOSE_PRIVATE—Intel
®
TXT Close Private Command
Register
The processor that authenticates the SEXIT code does this to prevent the Intel TXT
Private configuration space from being accessed using standard memory read/write
cycles.
General Behavioral Rules:
• This is a write-only register.
• This register is only available in the Private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
meaning.
3.6.1.8 TXT.VER.QPIIF
This register provides chipset version information. Important to MLE to detect/debug
chipsets.
Base: TXT_TXT Offset: 0048h
Base: TXT_PR Offset: 0048h
Bit Attr Default Description
7:0 WO 0h N/A
Base: TXT_TXT Offset: 0100h
Base: TXT_PR Offset: 0100h
Bit Attr Default Description
7:0 WO chipset revision ID