Datasheet

Processor Integrated I/O (IIO) Configuration Registers
166 Datasheet, Volume 2
3.6.1.5 TXT.ERRORCODE—Intel
®
TXT Error Code Register
When software discovers an error, it can write this scratch-pad register. However, the
register is sticky and reset only by a power-good reset, and so allows diagnostic
software (after the hard reset) to determine why the SENTER sequence failed (by
examining various status bits).
General Behavioral Rules:
This is a read-only register in the public Intel TXT configuration space.
This register is for read and write in the private Intel TXT configuration space.
Accesses to this register are done with 1-, 2-, or 4-byte writes and reads.
The default value of this register is 00000000h.
Access to this register has no other effect on the chipset other than reading or
writing the contents of this register.
3.6.1.6 TXT.CMD.RESET—Intel
®
TXT System Reset Command Register
When this command is invoked, the chipset resets the entire platform.
General Behavioral Rules:
This is a write-only register.
This register is only available in the private Intel TXT configuration space.
Accesses to this register are done with 1-byte writes.
The data bits associated with this command are undefined and have no specific
meaning.
Base: TXT_TXT Offset: 0030h
Base: TXT_PR Offset: 0030h
Base: TXT_PB_noWROffset: 0030h
Bit Attr Default Description
31:0 RWS 0h
TXT_ERRORCODE[31:0]
This register is a scratch pad register and is defined by the software usage
model.
Base: TXT_TXT Offset: 0038h
Base: TXT_PR Offset: 0038h
Bit Attr Default
Description
7:0 WO 0h N/A