Datasheet

Processor Integrated I/O (IIO) Configuration Registers
154 Datasheet, Volume 2
3.5.2.25 INV_COMP_EVT_UPRADDR[0:1]—Invalidation Completion
Event Upper Address Register
3.5.2.26 INTR_REMAP_TABLE_BASE[0:1]—Interrupt Remapping
Table Base Address Register
Register: INV_COMP_EVT_UPRADDR[0:1]
Addr: MMIO
BAR: VTBAR
Offset: ACh, 10ACh
Bit Attr Default Description
31:0 RW 0
Address
Integrated I/O (IIO) supports extended interrupt mode and implements this
register.
RegisteR: INTR_REMAP_TABLE_BASE[0:1]
Addr: MMIO
BAR: VTBAR
Offset: B8h, 10B8h
Bit Attr Default Description
63:12 RW 0
Intr Remap Base
This field points to the base of the page-aligned interrupt remapping table. If the
Interrupt Remapping Table is larger than 4-KB in size, it must be size-aligned.
Reads of this field returns value that was last programmed to it.
11 RO 0
IA32 Extended Interrupt Enable mode is not supported. IA-32 system is
operating in legacy IA-32 interrupt mode. Hardware interprets only 8-bit APICID
in the Interrupt Remapping Table entries.
10:4 RV 0 Reserved
3:0 RW 0
Size
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.