Datasheet

Datasheet, Volume 2 153
Processor Integrated I/O (IIO) Configuration Registers
3.5.2.22 INV_COMP_EVT_CTL[0:1]—Invalidation Completion
Event Control Register
3.5.2.23 INV_COMP_EVT_DATA[0:1]—Invalidation Completion
Event Data Register
3.5.2.24 INV_COMP_EVT_ADDR[0:1]—Invalidation Completion
Event Address Register
Register: INV_COMP_EVT_CTL[0:1]
Addr: MMIO
BAR: VTBAR
Offset: A0h, 10A0h
Bit Attr Default Description
31 RW 1
Interrupt Mask (IM)
0 = No masking of interrupt. When a invalidation event condition is detected,
hardware issues an interrupt message (using the Invalidation Event Data &
Invalidation Event Address register values).
1 = This is the value on reset. Software may mask interrupt message
generation by setting this field. Hardware is prohibited from sending the
interrupt message when this field is set.
30 RO 0
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as:
• An Invalidation Wait Descriptor with Interrupt Flag (IF) field set completed,
setting the IWC field in the Fault Status register.
• If the IWC field in the Invalidation Event Status register was already set at
the time of setting this field, it is not treated as a new interrupt condition.
The IP field is kept set by hardware while the interrupt message is held
pending. The interrupt message could be held pending due to interrupt
mask (IM field) being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either:
1. Hardware issuing the interrupt message due to either change in the
transient hardware condition that caused interrupt message to be held
pending or due to software clearing the IM field.
2. Software servicing the IWC field in the Fault Status register.
29:0 RO 0 Reserved
Register: INV_COMP_EVT_DATA[0:1]
Addr: MMIO
BAR: VTBAR
Offset: A4h, 10A4h
Bit Attr Default Description
31:16 RO 0 Reserved
15:0 RW 0 Interrupt Data
Register: INV_COMP_EVT_ADDR[0:1]
Addr: MMIO
BAR: VTBAR
Offset: A8h, 10A8h
Bit Attr Default Description
31:2 RW 0 Interrupt Address
1:0 RO 0 Reserved