Datasheet

Processor Integrated I/O (IIO) Configuration Registers
152 Datasheet, Volume 2
3.5.2.20 INV_QUEUE_ADD[0:1]—Invalidation Queue Address
Register
3.5.2.21 INV_COMP_STATUS[0:1]—Invalidation Completion Status
Register
Register: INV_QUEUE_ADD[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 90h, 1090h
Bit Attr Default Description
63:12 RW 0
IRQ Base
This field points to the base of size-aligned invalidation request queue.
11:3 RV 0 Reserved
2:0 RW 0
Queue Size
This field specifies the length of the invalidation request queue. The number of
entries in the invalidation queue is defined as 2^(X + 8), where X is the value
programmed in this field.
Register; INV_COMP_STATUS[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 9Ch, 109Ch
Bit Attr Default Description
31:1 RV 0 Reserved
0 RW1CS 0
Invalidation Wait Descriptor Complete
Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF)
field set. Once set this field remains set till software clears it.