Datasheet

Datasheet, Volume 2 151
Processor Integrated I/O (IIO) Configuration Registers
3.5.2.17 PROT_HIGH_MEM_LIMIT[0:1]—Protected Memory Limit
Base Register
3.5.2.18 INV_QUEUE_HEAD[0:1]—Invalidation Queue Header
Pointer Register
3.5.2.19 INV_QUEUE_TAIL[0:1]—Invalidation Queue Tail Pointer
Register
Register: PROT_HIGH_MEM_LIMIT[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 78h, 1078h
Bit Attr Default Description
63:21 RWL 0
HPD Limit
2-MB aligned limit address of the high protected DRAM (LPD) region
Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue,
invalidation queue read, invalidation status) themselves are allowed toward this
region, but no DMA accesses of any kind from any device is allowed toward this
region, when enabled.
This bit may be locked as RO in Intel Trusted Execution Technology (Intel TXT)
mode.
20:0 RV 0 Reserved
Register: INV_QUEUE_HEAD[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 80h, 1080h
Bit Attr Default Description
63:19 RV 0 Reserved
18:4 RO 0
Queue Head
Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be fetched next by hardware. This field is incremented after the
command has been fetched successfully and has been verified to be a
valid/supported command.
3:0 RV 0 Reserved
Register: INV_QUEUE_TAIL[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 88h, 1088h
Bit Attr Default Description
63:19 RV 0 Reserved
18:4 RW 0
Queue Tail
Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be written next by software.
3:0 RV 0 Reserved