Datasheet

Processor Integrated I/O (IIO) Configuration Registers
150 Datasheet, Volume 2
3.5.2.14 PROT_LOW_MEM_BASE[0:1]—Protected Memory Low
Base Register
3.5.2.15 PROT_LOW_MEM_LIMIT[0:1]—Protected Memory Low
Limit Register
3.5.2.16 PROT_HIGH_MEM_BASE[0:1]—Protected Memory High
Base Register
Register: PROT_LOW_MEM_BASE[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 68h, 1068h
Bit Attr Default Description
31:21 RWL 0
LPD Base
2-MB aligned base address of the low protected DRAM (LPD) region.
Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue,
invalidation queue read, invalidation status) themselves are allowed toward this
region, but no DMA accesses of any kind from any device is allowed toward this
region, when enabled.
This bit may be locked as RO in Intel
TXT mode.
20:0 RV 0 Reserved
Register: PROT_LOW_MEM_LIMIT[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 6Ch, 106Ch
Bit Attr Default Description
31:21 RWL 0
LPD Limit
2-MB aligned limit address of the low protected DRAM (LPD) region
Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue,
invalidation queue read, invalidation status) themselves are allowed toward this
region, but no DMA accesses of any kind from any device is allowed toward this
region, when enabled.
This bit may be locked as RO in Intel
TXT mode.
20:0 RV 0 Reserved
Register: PROT_HIGH_MEM_BASE[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 70h, 1070h
Bit Attr Default Description
63:21 RWL 0
HPD Base
2-MB aligned base address of the high protected DRAM (LPD) region.
Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue,
invalidation queue read, invalidation status) themselves are allowed toward this
region, but no DMA accesses of any kind from any device is allowed toward this
region, when enabled.
This bit may be locked as RO in Intel
TXT mode.
20:0 RV 0 Reserved