Datasheet

Datasheet, Volume 2 149
Processor Integrated I/O (IIO) Configuration Registers
3.5.2.10 FLTEVTDATA[0:1]—Fault Event Data Register
3.5.2.11 FLTEVTADDR[0:1]—Fault Event Address Register
3.5.2.12 FLTEVTUPRADDR[0:1]—Fault Event Upper Address Register
3.5.2.13 PMEN[0:1]—Protected Memory Enable Register
Register: FLTEVTDATA[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 3Ch, 103Ch
Bit Attr Default Description
31:16 RO 0 Reserved
15:0 RW 0 Interrupt Data
Register: FLTEVTADDR[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 40h, 1040h
Bit Attr Default Description
31:2 RW 0
Interrupt Address
The interrupt address is interpreted as the address of any other interrupt from a
PCI Express port.
1:0 RO 0 Reserved
Register: FLTEVTUPADDR[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 44h, 1044h
Bit Attr Default Description
31:0 RW 0
Address
Integrated I/O supports extended interrupt mode and hence implements this
register.
Register: PMEN[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 64h, 1064h
Bit Attr Default Description
31 RWL 0
Enable Protected Memory, as defined by the PROT_LOW(HIGH)_BASE and
PROT_LOW(HIGH)_LIMIT registers.
This bit may be locked as RO in Intel
TXT mode.
30:1 RV 0 Reserved
0RO 0
Protected Region Status
This bit is set by IIO whenever it has completed enabling the protected memory
region per the rules stated in the Intel
VT-d spec.