Datasheet
Processor Integrated I/O (IIO) Configuration Registers
148 Datasheet, Volume 2
3.5.2.9 FLTEVTCTRL[0:1]—Fault Event Control Register
Register: FLTEVTCTRL[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 38h, 1038h
Bit Attr Default Description
31 RW 1
Interrupt Message Mask (IMM)
0 = Software has cleared this bit to indicate interrupt service is available. When
a faulting condition is detected, hardware may issue a interrupt request
(using the fault event data and fault event address register values)
depending on the state of the interrupt mask and interrupt pending bits.
1 = Hardware is prohibited from issuing interrupt message requests.
30 RO 0
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as when an interrupt condition occurs when hardware
records a fault through one of the Fault Recording registers and sets the PPF
field in Fault Status register.
• Hardware detected error associated with the Invalidation Queue, setting the
IQE field in the Fault Status register.
• Hardware detected invalidation completion time-out error, setting the ITE
field in the Fault Status register.
• If any of the above status fields in the Fault Status register was already set
at the time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept set by hardware while the interrupt message is held pending.
The interrupt message could be held pending due to interrupt mask (IM field)
being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either:
1. Hardware issuing the interrupt message due to either change in the
transient hardware condition that caused interrupt message to be held
pending or due to software clearing the IM (Interrupt Mask) field in
Section 3.5.2.22.
2. Software servicing all the pending interrupt status fields in the Fault Status
register.
— PPF field is cleared by hardware when it detects all the Fault
Recording registers have Fault (F) field clear.
— Other status fields in the Fault Status register is cleared by software
writing back the value read from the respective fields.
29:0 RO 0 Reserved