Datasheet

Datasheet, Volume 2 145
Processor Integrated I/O (IIO) Configuration Registers
3.5.2.5 GLBSTS[0:1]—Global Status Register
3.5.2.6 ROOTENTRYADD[0:1]—Root Entry Table Address Register
(Sheet 1 of 2)
Register: GLBSTS[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 1Ch, 101Ch
Bit Attr Default Description
31 RO 0
Translation Enable Status
When set, this bit indicates that translation hardware is enabled and when
clear indicates the translation hardware is not enabled.
30 RO 0
Set Root Table Pointer Status
This field indicates the status of the root- table pointer in hardware.
29 RO 0 Reserved (N/A to IIO)
28 RO 0 Reserved (N/A to IIO)
27 RO 0 Reserved (N/A to IIO)
26 RO 0
Queued Invalidation Interface Status
IIO sets this bit once it has completed the software command to enable the
queued invalidation interface. Till then this bit is 0.
25 RO 0
Interrupt Remapping Enable Status
IIO sets this bit once it has completed the software command to enable the
interrupt remapping interface. Till then this bit is 0.
24 RO 0
Interrupt Remapping Table Pointer Status
This field indicates the status of the interrupt remapping table pointer in
hardware. This field is cleared by hardware when software sets the SIRTP field
in the Global Command register. This field is set by hardware when hardware
completes the set interrupt remap table pointer operation using the value
provided in the Interrupt Remapping Table Address register.
23:0 RV 000000h Reserved
RegisteR: ROOTENTRYADD[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 20h, 1020h
Bit Attr Default Description
63:12 RW 0
Root Entry Table Base Address
4-K aligned base address for the root entry table. Processor does not utilize
bits 63:36 and checks for them to be 0. Software specifies the base address
of the root-entry table through this register, and enables it in hardware
through the SIRTP field in the Global Command register. Reads of this register
returns value that was last programmed to it.
11:0 RV 0 Reserved